1. Field of the Invention
The present invention relates to a power supplying device in a primary side of a power circuit and, more particularly, to a power supplying device in a primary side of a power circuit of a display monitor to which a display power management signalling (DPMS) mode is applied, the power supplying device protecting a transistor from thermal damage due to voltage drop.
2. Discussion of Related Art
Recently, a variety of electric products and electronic products have been spread, and their consumption powers have become lower with the development of electric and electronic technologies. Among these products, a display monitor, for displaying data of a personal computer (PC) as visual images, uses high voltage for displaying the data. Accordingly, display monitor manufacturers are making their efforts to reduce the power consumed in the display monitor using high voltage and to apply VESA standard or like to the display monitor. A conventional display monitor to which the VESA standard is applied is explained below with reference to the attached drawing.
FIG. 1 is a block diagram of an inner circuit of a conventional display monitor. Referring to FIG. 1, a PC 100 includes a CPU 110 for receiving and processing a keyboard signal, and generating data according to the result processed, and a video card 120 for receiving the data from CPU 110, processing it to generate an image signal (R,G,B), and outputting a horizontal synchronous signal H-SYNC and vertical synchronous signal V-SYNC for synchronizing the image signal (R,G,B). A monitor 200, which receives the image signal, horizontal and vertical synchronous signals H-SYNC and V-SYNC output from video card 120 included in PC 100, comprises a microcomputer 210 for receiving the horizontal and vertical synchronous signals to judge resolution, a control button 220 for generating a picture control signal for controlling a display monitor picture and outputting it, a horizontal and vertical output circuit 230 for receiving the monitor picture control signal from microcomputer 210 and a reference oscillation signal, to synchronize raster, a video circuit 240 for receiving the image signal (R,G,B) from video card 120, amplifying and displaying it, and a power circuit 250 for supplying drive voltage to microcomputer 210, horizontal and vertical output circuit 230 and video circuit 240.
Inner blocks of display monitor 200 are described below in more detail. The horizontal and vertical synchronous signals H-SYNC and V-SYNC output from video card 120 of PC 100 are applied to microcomputer 210 storing various picture control data. Microcomputer 210 outputs an image control signal for controlling an image displayed on the monitor picture and the reference oscillation signal according to the picture control signal applied from control button 220. The image control signal and reference oscillation signal are sent from microcomputer 210 to a horizontal and vertical oscillation signals processor 230-1 which applies a vertical pulse for controlling the switching speed of on/off operation of a sawtooth generating circuit to a vertical drive circuit 230-2 according to the horizontal and vertical synchronous signals supplied from video card 120.
Vertical drive circuit 230-2, which received the vertical pulse, generally employs an one-stage vertical amplifying type, or emitter follower type in which a signal is input to the base of transistor and output from its emitter. Accordingly, it improves linearity rather than gain. Vertical drive circuit 230-2 sends a current signal to a vertical output circuit 230-3 which generates sawtooth current which flows through a V-DY 230-4, corresponding to a vertical synchronous pulse, determining a vertical scanning cycle. Horizontal and vertical oscillation signals processor 230-1 outputs a horizontal oscillation signal to a horizonal drive circuit 230-5 which supplies current sufficient for turning on/off a horizonal output circuit 230-6. Horizontal drive circuit 230-5 is divided into an in-phase (the same polarity) mode in which the output port is turned on when the drive port is turned on, and reverse phase (reverse polarity) mode, being currently widely used, in which the output port is turned off when the drive port is turned on. Horizontal output circuit 230-6, which received current from horizontal drive circuit 230-5 having the above characteristics, generates sawtooth current and sends it to an H-DY 230-7. This sawtooth current determines a horizontal scanning cycle.
To supply a stable DC voltage to the anode of a cathode ray tube (CRT) 240-4, a flyback collector according to a flyback transformer (FBT) 230-9 is employed and harmonics according to leakage inductance and distributed capacity of high voltage circuit 230-8 are used, to generate high voltage and apply it to anode port 240-4-1 of CRT 240-4, even though the collector pulse is small. Anode port 140-4-1 creates high voltage on the anode surface according to the applied high voltage, to control the luminance of the image signal (R,G,B) amplified by image signal processor 240. Here, an OSD 240-1 of image signal processor 240 receives OSD data in accordance with the picture control from microcomputer 210, to output an OSD gain signal.
The OSD gain signal output from OSD 240-1 and the image signal (R,G,B) applied from video card 120 are sent to a video pre-amplifier 240-2 which amplifies the low-level image signal (R,G,B) with a low voltage amplifier, maintaining a specific level of voltage of the signal. For example, a signal below 1 Vpp (peak to peak voltage) is amplified to 4-6 Vpp. A video output amplifier 240-3 amplifies the pre-amplified signal of 4-6 Vpp to 40-60 Vpp, supplying energy to each pixel of the display. The image signal amplified by video output amplifier 240-3 is sent to the cathode of CRT 240-4, to be converted into electron beam, displaying an image according to the image signal on the picture of the monitor.
In case of selection of OSD, the OSD is selected by video pre-amplifier 240-2, amplified to a predetermined level, and finally amplified by video output amplifier 240-3, displaying the OSD data on the picture of CRT 240-4. The OSD data displayed on CRT 240-4 provides a user of display monitor 200 with functions of the monitor or information on the monitor. Power circuit 250, which supplies drive voltage for displaying the image signal on the display monitor picture, receives alternating current (AC) through an AC input terminal 250-1 to which common AC is applied. A degaussing coil 250-2 receives the AC through AC input terminal 250-1, and recovers colors spread by terrestrial magnetism or external conditions to the original colors. For example, when AC is applied to degaussing coil 250-2 for 2 to 9 seconds, DC component of magnetism formed on a shadow mask in display monitor 200 is dispersed. This recovers the color spread caused by inexact deflection of electron beam to fluorescent material due to the DC component of magnetism.
DC rectified by a rectifier 250-3 is applied to a switching transistor 250-4. With the application of DC, switching transistor 250-4 performs switching operation to supply various drive voltages required for inner blocks of display monitor 200 through a voltage regulator 250-5. Here, a pulse width modulation (PWM) IC 250-6 controls turn on/off operations of switching transistor 250-4, to stabilize output voltage. Meantime, microcomputer 210 executes the DPMS mode based on VESA standard such as power off mode and suspend mode according to the detection of the horizontal and vertical synchronous signals, reducing the power consumed in display monitor 200. In this conventional display monitor 200, the power circuit to which the DPMS mode is applied is divided into a mode of supplying power to a primary side of the power circuit using a main power and auxiliary power, and a mode of supplying power to the primary side of the power circuit, the duty of PWM pulse in the main power being minimized. The second mode is explained below with reference to FIG. 2 showing a circuit diagram of the power circuit of FIG. 1.
As shown in FIG. 2, common power of AC is applied to ports IN1 and IN2 through AC input terminal 250-1 (shown in FIG. 1). The noise in the AC is filtered by a noise filter (not shown), and then the AC is rectified by a bridge diode 250-3a of rectifier 250-3. This rectified current is smoothed by a smoothing capacitor C1, to generate DC power at a resistor R1. The DC power is calculated by (DC power.apprxeq..sqroot.2.times.AC power), and the calculated DC power is supplied to PWM IC 250-6 (shown in FIG. 1) through a node (a). PWM IC 250-6 starts a main power transformer T1 of a switching transformer 250-4 according to the applied DC power. That is, the PWM pulse applied through PWM IC 50-6 repeatedly allows and blocks the current flow to a primary coil L1 of main power transformer T1, to induce current to a secondary coil L2. The current induced to the secondary coil L2 of the main power transformer T1 is rectified by a diode D1 and capacitor C2, to generate DC power, providing power to the primary side of the power circuit. Here, the DC power is supplied to the primary side, its voltage being dropped through a transistor Q1.
When the power off mode according to the DPMS mode is executed in the above power circuit, it is required that the consumption power is 5W in the power off mode, and 15W in the suspend mode. To satisfy this, on duty of the PWM pulse output through PWM IC 250-6 should be minimized. However, in case of wrong power circuit design, it is impossible to satisfy the DPMS standard even if the on duty of PWM pulse is minimized. When the consumption power becomes below 5W in the power off mode owing to the minimized PWM pulse duty, power at a point (b) is required to be higher than power at a point (c) (power of the primary side) to enable the normal operation. For example, in the normal operation, the voltage at point (b) must be 80V when the voltage at point (c) is 12V. Furthermore, in the power off mode, the voltage at point (b) must be 14V when the voltage at point (c) is 12V. Thus, the turn ratio of secondary coil L2 of transformer T1 should be determined to allow the potential at point (b) to be considerably higher than the potential at point (c) in the normal mode. Accordingly, to supply the voltage at point (b) to the primary side of the power circuit, large amount of voltage drop is needed. Transistor Q1 for dropping large amount of voltage emits heat corresponding to the amount of dropped voltage, and thus transistor Q1 needs large heat sink to emit the heat due to the voltage drop. Furthermore, the transistor may be destructed due to the heat, shortening its life.